Why Filter/Buffer gates?

[Gurgel]

1 hour ago, Saturnus said:

The terms buffer and filter predates modern logic gates and transistors. They arise from the basic function they serve:

The basic purpose of a buffer is to keep a signal turned on even if subjected to input signal cuts, and only turn off after a certain time with no input signal.

The basic purpose of a filter is to keep a signal turned off even if subjected to input signal spikes, and only turn on after a certain time with sustained input signal.

I agree. And that is why the terminology is good. Sure, you still have to read the description. I have to every time, despite about 35 years of experience with electronics, digital logic, some PLC coding (Very early products, anybody remember what a GAL is?) and coding on all abstraction levels. But that does not pose a real problem IMO. And the visual feedback you get when watching these things in action is quite adequate.

Somebody said something about it not being able to delay a digital signal. That is correct. For that you need something far more complex than just these two monoflop variants. What you need for actual signal delay was classically solved for example by sending the signal through a medium where sound is slow. PAL televisions did this with some form of large crystal sheet and a Piezo crystal for sender and receiver. A digital version would use a shift-register and that one is always clocked, adding a ton of issues. Hence I very well understand that actual signal delay is not available. If we had that controller component programmable in LUA ("Microcontroller Update"?) it would be pretty easy to do, just emulate that shift register with a ring-buffer. But as it is it is basically impossible to do. Well, maybe a long chain of NOT gates would work.

[Yunru]

1 minute ago, Gurgel said:

But as it is it is basically impossible to do.

But I can build working versions for any signal who's on and off states last for longer than ... whatever the lowest setting a buffer/filter can be set to.

[pacovf]

25 minutes ago, Yunru said:

Exactly, that's what I meant by maximum. If you had it set to something less than 5, say 2.5 (because easy numbers), and had 4 of them, it'd delay each signal by 10 seconds, without running into disruptions. (Right?)

Ah, I misunderstood your original post. Yes, that would work, though it still sets a limit on the minimum length of a signal you can delay. It’s just something to be aware when setting up your logic circuits.

[Gurgel]

8 minutes ago, Yunru said:

But I can build working versions for any signal who's on and off states last for longer than ... whatever the lowest setting a buffer/filter can be set to.

Sure. That you can do. But anything shorter will get filtered out.

[Yunru]

4 minutes ago, Gurgel said:

Sure. That you can do. But anything shorter will get filtered out.

Well I can also make a 1-tick one by inverting the filter and buffer and adding a ... my lack of technical knowledge is acting against me here... pulse converter?

But yeah, anything in between is only possible by exploiting a gate's input delay. 

And even then it depends on it staying off for longer than the filter so yeah, ignore all of the above.

[pacovf]

12 minutes ago, Gurgel said:

 Well, maybe a long chain of NOT gates would work.

This reminds me of a Zachtronics game, KOHCTPYKTOP (it used to be free online, not sure if it’s still the case). It is about integrated circuit designs, and one of the early levels tasked you with building an input delayer. The solution was to stack multiple NOT gates one after another. I would have never come up with it by myself. In fact, I didn’t get very far with it at all, not being an electrical engineer myself.

[Gurgel]

The not delay chain works, just tried it. From a completely ad-hoc test at 1x speed with 49 gates and a stop-watch, I deduce they have pretty exactly 100ms delay each. I did manage to get 2 different length impulses to travel in a loop.

Same delay for chained AND and OR gates.

 

33 minutes ago, pacovf said:

This reminds me of a Zachtronics game, KOHCTPYKTOP (it used to be free online, not sure if it’s still the case). It is about integrated circuit designs, and one of the early levels tasked you with building an input delayer. The solution was to stack multiple NOT gates one after another. I would have never come up with it by myself. In fact, I didn’t get very far with it at all, not being an electrical engineer myself.

Well, I am not an EE either, but I did start with gate-logic when I was 14 or so. That helps with this kind of thing

 

37 minutes ago, Yunru said:

But yeah, anything in between is only possible by exploiting a gate's input delay. 

Not really an exploit. Real-world applications are limited and there are some hoops to jump through, but for some applications these are used.

[Moonshade]

I get the buffer slightly it’s just that a buffer gate on logic lvl delays in signal completely for one iteration. So it’s state low is delayed and state high is delayed.

https://en.wikichip.org/wiki/buffer_gate

As for a filter if look just at how often it gets used in all the different places it gets used:

https://en.m.wikipedia.org/wiki/Filter

 all those filters have in common that they separate the unwanted stuff from the wanted over a continuous time. Which I don’t see happening in the filter implemented in oni it just wait until a set amount of time and then go’s high until it’s input is low.

a simple coffee filter doesn’t let nothing through until it received hot water for 30 seconds and then it will drop the water and the crushed beans together, well maybe I’m wrong about that I haven’t made coffee in quite a while.

in digital circuitry I expect a filter without to filter “noise” which is short high spikes in an low signal and sudden on a high signal sudden short  lows.

thats why I got different ideas about the buffer and filter.

I’m fine with the naming I just accept how things work and be done with it.

if people call a chair a table I’ll just sit on the table.

[Gurgel]

1 minute ago, Moonshade said:

I get the buffer slightly it’s just that a buffer gate on logic lvl delays in signal completely for one iteration. So it’s state low is delayed and state high is delayed.

https://en.wikichip.org/wiki/buffer_gate

That is actually a level-buffer, not a "time buffer". It is used to decouple input from output, as line-driver (when you have high load or long lines) and the like. In digital electronics, when calling something a "buffer", you usually mean this type of level buffer. 

The thing you would use on electronics side is this here: https://en.wikipedia.org/wiki/Monostable, called "monostable multivibrator", "monoflop" or "one shot". The Klei version is also "level triggered", i.e. the delay starts only when the input goes "inactive".