logic gates launches "invalid port overlap" error if a bridge end is upon the vacant tile of the logic gate


Gwido
  • Branch: Live Branch Version: Windows Known Issue

First a screen of the automation circuit :

20190315063522_1.thumb.jpg.e526646af9e0647b14c4be9cb5e90c43.jpg

The memory toggle on the right says there's an invalid port overlap. But the only overlap came from the bridge, and it's not upon one of the port of the memory toggle. :(

 

I tried in sandbox mode with the AND gate, and the same behavior occurs.

20190315064244_1.thumb.jpg.dc790406e644c7ea2f946e13d8cfd935.jpg

Also note on the memory toggle on the right that breaking the bridge do not remove the error. :-/

 

Hebe.sav


Steps to Reproduce
Build a logic gate. Put a bridge with one end on the tile where the logic gate don't have port. Remove the bridge to see that the error do not disappear.

Status: Known Issue

We are aware of this issue and have it logged internally but either we do not have a fix ready yet or we are not planning on addressing the issue in the immediate future.


  Report Bug


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