logic gates launches "invalid port overlap" error if a bridge end is upon the vacant tile of the logic gate


Gwido
  • Branch: Live Branch Version: Windows Known Issue

First a screen of the automation circuit :

20190315063522_1.thumb.jpg.e526646af9e0647b14c4be9cb5e90c43.jpg

The memory toggle on the right says there's an invalid port overlap. But the only overlap came from the bridge, and it's not upon one of the port of the memory toggle. :(

 

I tried in sandbox mode with the AND gate, and the same behavior occurs.

20190315064244_1.thumb.jpg.dc790406e644c7ea2f946e13d8cfd935.jpg

Also note on the memory toggle on the right that breaking the bridge do not remove the error. :-/

 

Hebe.sav


Steps to Reproduce
Build a logic gate. Put a bridge with one end on the tile where the logic gate don't have port. Remove the bridge to see that the error do not disappear.
  • Like 1


User Feedback


.... ....

sadly the same and it causes the bug, when bridges got TRUE after loading level
So it not allows me to build compact array of counters like this (yeah, i would prefer vanilla switch with 2 tiles)

 

58U0_3pqhmste8V7HfPxNnDFgFEZQndgGuTzE3Az

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I'm curious, can we know how Klei is planning to "fix" this?  Are we ultimately going to be allowed to use bridges that terminate on the unused portion of logic gates, or are we going to be prevented from building bridges if they terminate there?

I hope it's the former, but I need to be prepared if it's the latter.  Also, it seems for some weird reason memory toggles are not affected by the bug?

Edited by cblack

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I can confirm this is still an issue, though in my case I noticed no problems, other than the invalid port overlap message itself.

2019-10-07.png

Edited by NinjaWafflesOfDooM

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