Conveyor Splitter v2.0

[Meltdown]

Conveyor Splitter is a contraption than allows to split the contents of a single conveyor into multiple conveyors in defined ratios. It can be used to distribute resources between asteroids according to their demands.

For example, it can be used to set up centralized production of food on one asteroid, and distribute it among several other asteroids in proportion of their dupe count. Food can be substituted with any other consumable resource - reed fiber, glass, sand - the principle is the same.

The original Conveyor Splitter was based on Element Sensors and Couners. You may check out that build in this post:

The original setup was costly and took a lot of space, mainly due to logical part. This version is much more compact, and requires notably less refined metal.

How does it work?

Conveyor Splitter v2.0 is based on Conveyor Limiters counting passed cargo and temporary blocking access to rails in order to enforce target cargo ratio.

For example, let's imagine that there are two rails, and cargo has to be distributed between them in the ratio X:Y. In other words, for each X kg of cargo coming to the first rail, the second rail should receive Y kg. This can be achieved by having each rail go through Conveyor Limiter, with one rail having Limiter set to X kg, and the other limiter is set to Y kg. Both limiters should be set to unblock each time both of them become blocked. That way, once the first rail passes X kg of cargo, access to it becomes blocked until second rail passes Y kg of cargo.

The setup

I decided to use 3-rail version as an example. The number of rails can be easily adjusted, and there are no limits on the amount of rails this setup can support.

The conveyor part

Each output rail has a corresponding "branch" from the main line. Each branch has a priority-flow Conveyor Limiter that connects it to the output and a bridge that leads back into an input conveyor rail. "Branching" and backflow bridges are essential. This allows redirecting cargo packets back from blocked Limiters into main line. Simply placing Limiters on the main line and utilizing priority-flow results in "leaking" packets, while this build prevents such behaviour.

Conveyor part without Limiters and Bridges

The logic part

All Conveyor Limiters should reset the moment the last of them blocks. In order to achieve this, each Conveyor Limiter has its output negated, and connected to a single common wire, which is connected to Limiters reset port through NOT gate. While Conveyor Limiters are unblocked, each of them outputs Red Signal. Negated signals become Green, and wire with multiple Green Signals outputs Red Signal through NOT gate. When Limiter blocks, it's negated signal becomes Red. When all Limiters are blocked, the common wire turns Red, turning NOT gate output Green. Reset ports receive Green signal and unblock Limiters, which instantly turns the reset signal back to Red.

That's it! I hope you enjoyed this post and this build would be useful for you.

[Gurgel]

I like your use of a 3 input "wired" OR gate to make a 3-input AND!

[ghkbrew]

 

5 hours ago, Gurgel said:

I like your use of a 3 input "wired" OR gate to make a 3-input AND!

De Morgan's Laws are great form minifying automation logic.

[JRup]

13 minutes ago, ghkbrew said:

 

De Morgan's Laws are great form minifying automation logic.

Well, that too. In this case we're seeing NOR logic to build the item the game doesn't give us.

This one helps too: http://www.uop.edu.pk/ocontents/Lec-10-universal gates.pdf

[ghkbrew]

43 minutes ago, JRup said:

Well, that too. In this case we're seeing NOR logic to build the item the game doesn't give us.

I dunno, NOT(OR(NOT(p), NOT(q), NOT(r))) being equivalent to AND(p, q, r) is sort of the definition of a De Morgan law (plus double negation).  I'd say NOR is a universal logic gate because of the logical equivalencies like De Morgan's laws.  Or perhaps they're both manifestations of the same underlying logical structure.

[JRup]

3 minutes ago, ghkbrew said:

Or perhaps they're both manifestations of the same underlying logical structure.

In short: these are practical applications of DeMorgan's laws.

For digital circuits we get to use either NOR or NAND logic to build any other circuit/component if we're missing a resource. In the case of this game, pooling any output into a single line behaves mostly like a natural OR gate (with its limitations, of course) and we got the logic to help us with the end result. Win-win.

 

[Gurgel]

8 hours ago, ghkbrew said:

De Morgan's Laws are great form minifying automation logic.

They are. But they are almost "lost knowledge" these days, except for EEs. So it is always nice seeing somebody using them competently.

7 hours ago, JRup said:

In the case of this game, pooling any output into a single line behaves mostly like a natural OR gate (with its limitations, of course) and we got the logic to help us with the end result.

That one is called a "wired OR", because it is implemented with wires. Today it would probably be called a "virtual OR" or some such nonsense. Whether that approach is possible/reliable depends on the logic hardware. Typical TTL logic restricts this to only "OR" and open collector/open drain outputs which do only have input current and optional use of a discrete pull-up resistor (not really needed with x-TTL, but improves noise-immunity).

The historic reason is that NPN Transistors (the drivers towards ground) have much better properties than PNP transistors (the drivers towards logic high voltage). With modern FETs that is still true, but it is much easier putting a bit more effort in the upper-side driver (P-FET) to make it match the N-FET driving towards ground in its properties. That is why most modern logic signals are basically symmetrical. 

As a side-note: NAND (or more rarely NOR) as basis if a logic system happened because TTL and CMOS logic can do NAND/NOR more naturally than AND/OR. In fact, AND/OR gets implemented by doing NAND/NOR and adding an inverter which is an 1-input NAND/NOR gate. You can even see in the datasheets that AND/OR gates are a bit slower than NAND/NOR as a result. 

[JRup]

6 hours ago, Gurgel said:

But they are almost "lost knowledge" these days, except for EEs

It is also mandatory for CS where I'm from, it is ironically somewhat hidden from EEs here... Don't worry, this arcane knowledge will survive through these trying times.