Mehbark

Significantly improved Automation compression/Decompression or S.A.D.

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Mehbark    60
On 2/21/2020 at 6:47 PM, psusi said:

Do those clocks remain in sync across save/load cycles?

Good question. In my limited testing, they've been fine, but I'd like the clocks to have a reset port so I can hook them up to a cycle sensor. 

Edited by Mehbark

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psusi    188

Did you build them with debug mode and the game paused?  i.e. if you build them at different times, will they be out of sync?

 

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Mehbark    60
1 minute ago, psusi said:

Did you build them with debug mode and the game paused?  i.e. if you build them at different times, will they be out of sync?

 

I built them in sandbox mode paused and unpaused. If you build them at different times they will be out of sync, but you can pause the game and reset the clocks and counters after they are both built. 

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Saturnus    3,534
26 minutes ago, Mehbark said:

I built them in sandbox mode paused and unpaused. If you build them at different times they will be out of sync, but you can pause the game and reset the clocks and counters after they are both built. 

But as you said without a reset input port you have to keep an eye on it and adjust it manually if/when they go out of sync again.

So if I were you I'd use a standard oscillator or pulse generator set up instead of a timer. At least you inherently have a reset on those.

Edited by Saturnus

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Mehbark    60
 
 
 
 
5 minutes ago, Saturnus said:

So if I were you I'd use a standard oscillator or pulse generator set up instead of a timer. At least you inherently have a reset on those.

To be perfectly honest, I don't know how to make one of those. :p

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Saturnus    3,534
36 minutes ago, Mehbark said:

To be perfectly honest, I don't know how to make one of those. :p

Tie a NOT gate and a filter (or buffer) gate together.

Here's a quick version I threw together. The switch in the middle is the reset input line.

SAD.thumb.png.347f6faadef4d9dbf9d11622df7e5fd2.png

 

Edited by Saturnus
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Mehbark    60
27 minutes ago, Lbphero said:

Im confused, this is logic for door compressors?

This is logic for translating four inputs to one output and then translating that into four identical outputs.

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pether    121
34 minutes ago, Lbphero said:

Im confused, this is logic for door compressors?

No, it is for data compression - a method to write 4 bits of data using 1 bit wire by the cost of some update delay. You can also use it to compress 16 bit data on single 4-bit ribbon. Tbh I currently have no idea where you can apply this tool, but once you will need it - here it is :) 

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Saturnus    3,534

Technically speaking it's a Serdes (serializer/deserializer) interface.

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kezat    0

One could add a 5th "data line" with a power wire and watt sensor :) Might work well to synchronize each end using it as a clock pulse.

Edited by kezat

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Gurgel    1,387
On 2/23/2020 at 3:36 AM, Saturnus said:

Technically speaking it's a Serdes (serializer/deserializer) interface.

Actually, it is called Time Division Multiplexing (TDM).

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Derringer    30
19 hours ago, Gurgel said:

Actually, it is called Time Division Multiplexing (TDM).

Yup. Don't know if they are called that in-game, but those new 4-way gadgets are multiplexer and demultiplexer 'gates'. I almost did a spit-take when I first saw them in screenshots, because I totally missed the announcement for the automation update. Do muxes remember their current index across save/load? If so, they might also be an efficient and stable core for a clocked flip-flop type like D or JK.

Edited by Derringer

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Gurgel    1,387
3 hours ago, Derringer said:

Do muxes remember their current index across save/load? If so, they might also be an efficient and stable core for a clocked flip-flop type like D or JK.

Interesting idea! Because everything has a state and is clocked in ONI, they might.

 

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Derringer    30

An R-S flip-flop (the game calls it a memory toggle) is not clocked; clocked flip-flops don't change their output until they receive a pulse on an additional 'clock' input.

The clocked counterpart of R-S is the J-K flip-flop which has 3 inputs. The difference is that while R or S change the output state immediately, J and K do not; the output only changes when CK goes from green to red. If J is green, CK can change the output from red to green; if K is green, CK can change the output from green to red. If both J and K are green, CK toggles the output Q. If neither one is green, CK has no effect.

There are other variants occasionally seen. The D flip-flop has D and CK inputs, and sets output Q equal to D when a pulse is received on CK. The T flip-flop toggles output Q when T is green and CK receives a pulse.

Then there's the all-purpose flip-flop type found in pairs in the old 7476 logic chip, with 5 inputs (R, S, J, K, CK) and 2 outputs (Q, ~Q). R and S ignore CK and directly set the output, J and K control CK pulse behaviour, ~Q is always the opposite of Q and they change at the same time. They're designed to be used in tandem to create things like multi-bit binary counters. T can be simulated by wiring up J and K together, D can be simulated by wiring J = D, K = not D.

Duplicants might prefer the more robust 5476 in industrial builds because it overheats at 125 °C, while the 7476 overheats at 70.

Edited by Derringer
temperature notes

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Gurgel    1,387
7 hours ago, Derringer said:

An R-S flip-flop (the game calls it a memory toggle) is not clocked; clocked flip-flops don't change their output until they receive a pulse on an additional 'clock' input.

This one is, because the whole logic-sim is clocked. You can see this by connecting an inverter input-to-output.

The real-wold analog is not clocked, agreed.

 

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psusi    188
3 hours ago, Gurgel said:

This one is, because the whole logic-sim is clocked. You can see this by connecting an inverter input-to-output.

The real-wold analog is not clocked, agreed.

 

A not gate always has a propagation delay so if you connect one back to itself, it will oscillate.

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Gurgel    1,387
1 hour ago, psusi said:

A not gate always has a propagation delay so if you connect one back to itself, it will oscillate.

No. A regular NOT gate will just go to an invalid value between 0 and 1 and stabilize. These things are actually pretty bad but very fast analog amplifiers and the propagation delay is just an equivalent value for a clean sqare-wave input signal. For an analog amplifier to oscillate you need a phase-shift of at least 360 degrees. A single inverter only supplies 180 degrees and its propagation delay in analog mode is basically just distance vs. light-speed and does not matter. It cannot actually oscillate that fast and hence does not. 

Be aware that _buffered_ NOT gates in CMOS (for example) are actually 3 NOT gates in a row and they usually will oscillate as the phase-shift needed is present. But a classical 7404 or an unbuffered CMOS inverter will not oscillate, unless you add additional circuitry.

A Schmitt-Trigger NOT will oscillate, but at a very high rate and it will be dependent on temperature, power supply, etc. It is significantly more complex than a regular inverter though and significantly slower. 

Interestingly, a single ONI NOT-gate seems to just output a constant "1" when looped. But put 3 of them in a loop and they oscillate at what seems pretty close to a  3/5 sec period i.e. 3 clock ticks. That means they are clocked by the tick. 

Edited by Gurgel

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Saturnus    3,534
2 hours ago, Gurgel said:

But put 3 of them in a loop and they oscillate at what seems pretty close to a  3/5 sec period i.e. 3 clock ticks. That means they are clocked by the tick. 

A tick is 1/10th of a second. You can confirm this by stringing 10 NOT in series and compare to a 1s filter gate.

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Gurgel    1,387
14 hours ago, Saturnus said:

A tick is 1/10th of a second. You can confirm this by stringing 10 NOT in series and compare to a 1s filter gate.

Does not matter. The point is they are not free-running.

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psusi    188
15 hours ago, Saturnus said:

A tick is 1/10th of a second. You can confirm this by stringing 10 NOT in series and compare to a 1s filter gate.

Every reference I've ever seen has said that a logic game tick is 1/5th of a second.  I think they changed something with NOT gates a few patches back so that they act like they have no delay.  I believe this means that the signal propagates through the NOT gate without needing to be clocked in and then out on the next clock.  I bet this only works once, and so effectively, your string of NOT gates is halved, and the signal only needs 5 ticks to go through.

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Saturnus    3,534
8 minutes ago, psusi said:

I think they changed something with NOT gates a few patches back so that they act like they have no delay. 

Positive edge detectors still work, so not that.

It is possible it used to be 1/5th of a second but the automation clock has been 0.1s for at least a year.

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Gurgel    1,387
33 minutes ago, psusi said:

Every reference I've ever seen has said that a logic game tick is 1/5th of a second.  I think they changed something with NOT gates a few patches back so that they act like they have no delay.  I believe this means that the signal propagates through the NOT gate without needing to be clocked in and then out on the next clock.  I bet this only works once, and so effectively, your string of NOT gates is halved, and the signal only needs 5 ticks to go through.

Would not surprise me. And it might explain why a single looped NOT gate just outputs a solid 1.

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