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Q the Platypus

Four channel multiplexer design

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Inspired by a discussion on this forum I decided to work on creating my own multiplexer.  This is an early design so far and there are is much room for improvements but I hope people will find this helpful.  There is nothing about this design that would prevent it from being used for any number of channels as long as it is a power of 2.

Spoiler

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 This is the main multiplexer. The two automation wires on the bottom left select which channel is active.  The not gate/and gate array is used to decode the binary representation of the channel into a signal that selects which and gate will allow which in coming single threw.  On the right you can see the data line and the clock line exiting the image.

Spoiler

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Here is the control system for the multiplexer.  The And gate s-r latch combination acts as a frequency divider/pulse counter.  The counter alternates between off and on with every pulse that it receives, however it only will output a pulse when it is in the "on" mode.  This means that by chaining these counters together it will cycle through the output of "00" "01" 10" "11".

Spoiler

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This is the demultiplexer that is used to undo the multiplexing.  It uses the same binary counting system as the multiplexer along with the same system to do channel selection.  After the channel selector the and with one input notted is used as an edge detector to reset the s-r latch briefly each time the that channel is switched to.

 

Limitations of this design.  It has no way to handle channel sync so if for some reason the states of the counters on each side get out of synchronisation things will get mapped to the wrong channels.

 

I would like to improve the design by going to a one wire design and using something like Manchester encoding to encode the clock signal inside of the data.  However in order to do this I'm going to need to create a phase detector and a variable frequency oscillator in order to create the clock signal re-generator.

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Yunru    778

[Insert comment about each gate also being a 1 tick buffer when I have more time]

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Gurgel    1,001

This is the standard digital multiplexer design. Should work in ONI as well.

 

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Arnadath    69

@Q the Platypus hey. It seems that i will have to freeze my project for more than the afforementioned 2 weeks. You seem interested in digital stuff. Would you like to continue it? I have too many real life stuff atm and got in the forum today to ask if anyone would like to make progress on it. 

 

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